The present invention relates to a memory control circuit which controls read access, accesses for reading, writing and so forth to a memory, such as a dynamic random access memory (hereinafter called “DRAM”).
A conventional memory control circuit has a core circuit which is provided between a central processing unit (hereinafter called “CPU”) and a DRAM and executes controls on the DRAM, such as refresh control, precharge control and access control in burst mode, in place of the CPU.
Further, the memory control circuit has test circuits respectively provided between the CPU and the core circuit and between the core circuit and the DRAM to test the functions of the core circuit.
Each test circuit includes an extension circuit which extends input test data of 8 bits to 32 bits, 4 times the size of the input test data, a selector which selects the extended data and data from the CPU or the DRAM and sends the selected data to the core circuit, and a degeneration circuit which compresses 32-bit data from the core circuit to 8-bit data and outputs the 8-bit data.
The core circuit has a control register of about 8 bits to set information, such as the capacity of the DRAM to be controlled and a bit width at the time of making access. Of 32-bit data to be input to the core circuit, lower 8-bit information is written in the control register. The contents of the control register become lower 8 bits in 32-bit data that is output from the core circuit.
In test mode, the extension circuit arranges 8-bit information to be set in the control register as lower data in 32-bit data and sends the resultant data to the input terminal of the core circuit. Therefore, predetermined information can be written in the control register.
In case of reading the contents of the control register in test mode, the read contents of the control register are output to lower 8 bits of 32-bit data of the output terminal of the core circuit. The 32-bit data output from the output terminal are compressed to 8-bit data by the degeneration circuit.
The degeneration circuit carries out data compression by performing logical calculation using 32-bit data, not simply discarding other bits than the lower 8 bits. This disables readout of the contents of the control register from. the degeneration circuit.